CONTENTS

  Title Page

  Copyright Page

  Preface

  1      Introduction

  1.1     Overview

  1.2     DRQ3B-A and DRQ3B-S

  2      Configuration and Installation

  2.1     Configuration
    2.1.1      Base Address
    2.1.2      Vector Address
    2.1.3      Interrupt Priority Level
    2.1.4      Extended Block Mode
    2.1.5      Holdoff Time Selection
      2.1.5.1      Revision Level C and Higher Revision Levels
      2.1.5.2      Revision Level B
    2.1.6      Terminator Resistor Packs
    2.1.7      Q/CD Jumpers

  2.2     Installation

  2.3     Diagnostics
    2.3.1      VAX Diagnostics
    2.3.2      PDP-11 Diagnostics

  3      Interfacing with the DRQ3B

  3.1     Overview

  3.2     DRQ3B-S Connectors

  3.3     Port Signals
    3.3.1      Data Signals
    3.3.2      Handshake Signals
    3.3.3      End-of-Process Signal
    3.3.4      External Interrupt Signal
    3.3.5      Initialization Output Pin
    3.3.6      Clear FIFO Pin
    3.3.7      General Purpose I/O Function Bits
    3.3.8      Ground Pins

  3.4     Parallel Port Line Logic

  3.5     Cabinet Kits

  3.6     Cables
    3.6.1      Loopback Cables

  3.7     Handshake Convention
    3.7.1      External Devices Handshaking Signal Names
    3.7.2      Input Handshaking
    3.7.3      Output Handshaking
    3.7.4      One-Wire Handshaking

  3.8     Terminator Resistor Packs

  4      Programming

  4.1     Programming Registers

  4.2     Performing DMA Transfers
    4.2.1      FIFO Port or Memory-to-Memory Transfers
    4.2.2      Hardware Request Line and Software Starts
    4.2.3      Block or Nonblock DMA Transfers
      4.2.3.1      Extended Block Mode Option
    4.2.4      Allocation of Memory Buffers
    4.2.5      Transfer with Compare
    4.2.6      Chain Loading
    4.2.7      Action at the End of DMA Transfer
      4.2.7.1      DMA Interrupts
      4.2.7.2      Base-to-Current Reloading
      4.2.7.3      Chain Reloading
    4.2.8      FIFO Interrupts

  4.3     Double Buffering
    4.3.1      Second Interrupt Pending
    4.3.2      Using EOP with Double Buffering
    4.3.3      Terminating Double Buffering

  4.4     Important Points About the DMA Logic

  4.5     Board Level Registers
    4.5.1      DMA Data Window Register and DMA Address Window Register
    4.5.2      Port Configuration Register
    4.5.3      Port Data Registers
    4.5.4      Transfer Count Register
    4.5.5      Status Register
      4.5.5.1      Clearing Interrupts in the Status Register
      4.5.5.2      DMA Interrupts
    4.5.6      Function Registers

  4.6     DMA Registers

  4.7     DMA Control Registers
    4.7.1      Master Mode Register
    4.7.2      Channel Mode Registers
      4.7.2.1      Channel Mode High Register
      4.7.2.2      Channel Mode Low Register
    4.7.3      Command Register

  4.8     Chaining Control Registers
    4.8.1      Chain Control Register
    4.8.2      Chain Address Segment Register
    4.8.3      Chain Address Offset Register

  4.9     Buffer Control Registers
    4.9.1      Current and Base Address Registers
      4.9.1.1      Current and Base Address Segment Register
      4.9.1.2      Current and Base Address Offset Register
    4.9.2       Current and Base Operation Count Registers

  4.10    Pattern Control Registers
    4.10.1     Pattern Register
    4.10.2     Mask Register

  4.11    Interrupt Control Registers
    4.11.1     DMA Status Register
    4.11.2     Interrupt Save Register

  4.12    Performing Programmed I/O

  A   Specifications

  A.1     Overview

  A.2     Factory Configuration

  A.3     Environmental Specifications

  A.4     Electrical Specifications
    A.4.1      Power Requirement
    A.4.2      Bus Loads
    A.4.3      I/O Drive Capability

  A.5     DMA Chip Reference

  A.6     Performance Specifications

  FIGURES

  1-1        DRQ3B Block Diagram

  2-1        The DRQ3B DMA Parallel I/O Module

  2-2        Switch Pack 0

  2-3        Correspondence of Switch Pack 0 Bits with Address Bits

  2-4        Switch Pack 1

  2-5        Correspondence of Switch Pack 1 Bits with Vector Address Bits

  3-1        Input Pins on J2 of the DRQ3B-A Cabinet Kits and DRQ3B-S J2 Connector

  3-2        Output Pins on J1 of the DRQ3B-A Cabinet Kits and DRQ3B-S J1 Connector

  3-3        Input Handshaking Signals Timing Diagram

  3-4        Output Handshaking Signals Timing Diagram

  4-1        DMA Data Window Register

  4-2        DMA Address Window Register

  4-3        Port Configuration Register

  4-4        Port 0 Data Register

  4-5        Port 1 Data Register

  4-6        Transfer Count Register

  4-7        Status Register

  4-8        Input Function Register

  4-9        Output Function Register

  4-10       Master Mode Register

  4-11       Channel Mode High Register

  4-12       Channel Mode Low Register

  4-13       Command Register

  4-14       Example of a Simple Chain Table

  4-15       Example of a Complete Chain Table

  4-16       Chain Control Register

  4-17       Chain Address Segment Register

  4-18       Chain Address Offset Register

  4-19       Current and Base Address Segment Register

  4-20       Current and Base Address Offset Register

  4-21       Current and Base Operation Count Register

  4-22       Pattern Register

  4-23       Mask Register

  4-24       DMA Status Register

  4-25       Interrupt Save Register

  TABLES

  2-1        Register Address Offsets

  2-2        Vector Address Offsets

  2-3        Interrupt Priority Level Switch Settings

  2-4        Holdoff Time Selection

  2-5        PDP-11 Diagnostic Module Names

  3-1        DRQ3B Cabinet Kits

  3-2        BC19T Twisted Pairs

  3-3        Terminator Resistor Packs

  4-1        DRQ3B Registers

  4-2        DRQ3B DMA Registers

  4-3        DMA Transfer Types

  4-4        DMA Data Window Register

  4-5        DMA Address Window Register

  4-6        Port Configuration Register

  4-7        Port Data Registers

  4-8        Transfer Count Register

  4-9        Status Register

  4-10       Status Register Commands

  4-11       Input Function Register

  4-12       Output Function Register

  4-13       Master Mode Register

  4-14       Channel Mode High Register

  4-15       Required Flip Bit Settings for FIFO Input/Output

  4-16       Flip Bit Settings in Memory-to-Memory Transfers

  4-17       Channel Mode Low Register

  4-18       Command Register

  4-19       Chain Control Register

  4-20       Chain Address Segment Register

  4-21       Chain Address Offset Register

  4-22       Current and Base Address Segment Register

  4-23       Base and Current Address Offset Register

  4-24       Current and Base Operation Count Register

  4-25       Pattern Register

  4-26       Mask Register

  4-27       DMA Status Register

  4-28       Interrupt Save Register