CONTENTS Title Page Copyright Page Preface 1 Introduction 1.1 The DRQ3B Parallel DMA I/O Module 1.2 The MicroVAX/DRQ3B Device Driver 2 Installation 2.1 Installation Prerequisites 2.2 Installation Time 2.3 Installation Procedure 2.4 Installation Verification Procedure - IVP 2.5 Post-Installation Tasks - MicroVMS Systems Only 2.6 Sample Installation Dialogue - MicroVMS V4.7 2.7 Sample Installation Dialogue - VMS V5.0 3 Operating Features 3.1 Block or Nonblock DMA Transfers 3.1.1 Extended Block Mode Option 3.2 Double Buffering 3.3 DMA I/O Transfer Modes - Logical and Physical 3.3.1 Logical I/O Operation 3.3.2 Physical I/O Operation 3.3.3 Advantages of Physical I/O 3.4 Using Logical I/O 3.4.1 Logical I/O Summary 3.5 Using Physical I/O 3.5.1 Physical I/O Read and Write Logical Blocks 3.5.2 Physical I/O to or from Local VAX Memory 3.5.2.1 Page Locking 3.5.2.2 Allocating Mapping Registers 3.5.2.3 Q-bus Address Descriptor 3.5.2.4 User Mapping Register Descriptor 3.5.2.5 Summary of Physical I/O to Local VAX Memory 3.5.3 Physical I/O to or from Q-bus Memory 3.5.3.1 Summary of Physical I/O to Q-bus Memory 3.6 Selecting I/O Mode 3.7 Interrupts and Attention AST's 3.7.1 End-of-Process 3.7.2 Channel 0 EOP 3.7.3 Nonexistent Memory EOP 3.7.4 External Interrupt 3.7.5 FIFO Underflow 3.7.6 FIFO Overflow 4 Function Codes and I/O Status Blocks 4.1 Definition Files 4.2 Function Codes, Arguments, and Modifiers 4.2.1 Function Codes 4.2.2 Function Code Arguments 4.2.2.1 Logical I/O Function Code Arguments 4.2.2.2 Physical I/O Function Code Arguments 4.2.3 Function Modifiers 4.2.3.1 IO$M_HX_NOBLOCK_MODE and IO$M_HX_NODOUBLE_BUFF 4.2.3.2 IO$M_HX_FIFO_CLEAR 4.2.3.3 IO$M_HX_NOSTART_DMA 4.2.3.4 IO$M_HX_RUN_DOWN 4.2.3.5 IO$M_HX_FUNCT_BITS and IO$M_HX_ATTN_ENABLE 4.3 Set Mode and Sense Mode 4.3.1 Controlling the Function Bits 4.3.1.1 Writing to the Output Function Bits 4.3.1.2 Reading the Input Function Bits 4.3.2 Enabling and Disabling Attention AST's 4.3.2.1 Interrupt Setting Summary 4.4 I/O Status Blocks 4.4.1 DMA Initialization I/O Status Block 4.4.2 Read/Write I/O Status Block 4.4.3 Set Mode/Sense Mode I/O Status Block 4.5 DRQ3B Status Registers 4.5.1 Status Register 4.5.2 DMA Status Register 4.6 Buffer Completion 4.6.1 AST Routines 4.6.2 Event Flags 4.6.3 SYS$QIOW 4.7 Using Both Ports Simultaneously 4.8 AST and DIO Limits 4.9 Timeouts 4.10 Canceling I/O 5 Device Information A Example Program A.1 Example Program B DRQ3B Connectors B.1 DRQ3B Connectors FIGURES 4-1 Attention Mask Format 4-2 DMA Initialization I/O Status Block 4-3 Read/Write I/O Status Block 4-4 SET MODE/SENSE MODE IOSB 4-5 High Word of the First Longword in SETMODE IOSB 4-6 Status Register 4-7 DMA Status Register B-1 Input Pins on J2 of the DRQ3B Connector Kits B-2 Output Pins on J1 of the DRQ3B Connector Kits TABLES 4-1 Definition Files 4-2 Function Codes for Logical I/O 4-3 Function Codes for Physical I/O 4-4 Function Code Arguments for Logical I/O 4-5 Function Code Arguments for Physical I/O 4-6 Function Modifiers for Logical and Physical I/O 4-7 Correspondence Between P1 Bits and Function Bits 4-8 Arguments for the IO$M_HX_ATTN_ENABLE Function Modifier 4-9 Attention AST Bit Masks 4-10 Attention AST Constants 4-11 Status Codes Returned by IO$_HX_DMA_INIT 4-12 Status Codes Returned by Read/Write Logical or Physical Block 4-13 Function Bit Status in SETMODE IOSB 4-14 Status Code Returned by IO$M_HX_FUNCT_BITS 4-15 Status Codes Returned by IO$M_HX_ATTN_ENABLE 4-16 Status Register 4-17 DMA Status Register 5-1 Device Information