CONTENTS Title Page Copyright Page Preface VAX MACRO Language 1 Introduction 2 VAX MACRO Source Statement Format 2.1 Label Field 2.2 Operator Field 2.3 Operand Field 2.4 Comment Field 3 Components of MACRO Source Statements 3.1 Character Set 3.2 Numbers 3.2.1 Integers 3.2.2 Floating-Point Numbers 3.2.3 Packed Decimal Strings 3.3 Symbols 3.3.1 Permanent Symbols 3.3.2 User-Defined Symbols and Macro Names 3.3.3 Determining Symbol Values 3.4 Local Labels 3.5 Terms and Expressions 3.6 Unary Operators 3.6.1 Radix Control Operators 3.6.2 Textual Operators 3.6.2.1 ASCII Operator 3.6.2.2 Register Mask Operator 3.6.3 Numeric Control Operators 3.6.3.1 Floating-Point Operator 3.6.3.2 Complement Operator 3.7 Binary Operators 3.7.1 Arithmetic Shift Operator 3.7.2 Logical AND Operator 3.7.3 Logical Inclusive OR Operator 3.7.4 Logical Exclusive OR Operator 3.8 Direct Assignment Statements 3.9 Current Location Counter 4 Macro Arguments and String Operators 4.1 Arguments in Macros 4.2 Default Values 4.3 Keyword Arguments 4.4 String Arguments 4.5 Argument Concatenation 4.6 Passing Numeric Values of Symbols 4.7 Created Local Labels 4.8 Macro String Operators 4.8.1 %LENGTH Operator 4.8.2 %LOCATE Operator 4.8.3 %EXTRACT Operator 5 VAX MACRO Addressing Modes 5.1 General Register Modes 5.1.1 Register Mode 5.1.2 Register Deferred Mode 5.1.3 Autoincrement Mode 5.1.4 Autoincrement Deferred Mode 5.1.5 Autodecrement Mode 5.1.6 Displacement Mode 5.1.7 Displacement Deferred Mode 5.1.8 Literal Mode 5.2 Program Counter Modes 5.2.1 Relative Mode 5.2.2 Relative Deferred Mode 5.2.3 Absolute Mode 5.2.4 Immediate Mode 5.2.5 General Mode 5.3 Index Mode 5.4 Branch Mode 6 VAX MACRO Assembler Directives .ADDRESS .ALIGN .ASCI x .ASCIC .ASCID .ASCII .ASCIZ .BLK x .BYTE .CROSS .DEBUG .DEFAULT .D_FLOATING .DISABLE .ENABLE .END .ENDC .ENDM .ENDR .ENTRY .ERROR .EVEN .EXTERNAL .F_FLOATING .G_FLOATING .GLOBAL .H_FLOATING .IDENT .IF .IF_x .IIF .IRP .IRPC .LIBRARY .LINK .LIST .LONG .MACRO .MASK .MCALL .MDELETE .MEXIT .NARG .NCHR .NLIST .NOCROSS .NOSHOW .NTYPE .OCTA .ODD .OPDEF .PACKED .PAGE .PRINT .PSECT .QUAD .REFn .REPEAT .RESTORE_PSECT .SAVE_PSECT .SHOW .SIGNED_BYTE .SIGNED_WORD .SUBTITLE .TITLE .TRANSFER .WARN .WEAK .WORD VAX Data Types and Instruction Set 7 Terminology and Conventions 7.1 Numbering 7.2 UNPREDICTABLE and UNDEFINED 7.3 Ranges and Extents 7.4 MBZ 7.5 RAZ 7.6 SBZ 7.7 Reserved 7.8 Figure Drawing Conventions 8 Basic Architecture 8.1 Basic Architecture 8.2 VAX Addressing 8.3 Data Types 8.3.1 Byte 8.3.2 Word 8.3.3 Longword 8.3.4 Quadword 8.3.5 Octaword 8.3.6 F_floating 8.3.7 D_floating 8.3.8 G_floating 8.3.9 H_floating 8.3.10 Variable-Length Bit Field 8.3.11 Character String 8.3.12 Trailing Numeric String 8.3.13 Leading Separate Numeric String 8.3.14 Packed Decimal String 8.4 Processor Status Longword (PSL) 8.4.1 C Bit 8.4.2 V Bit 8.4.3 Z Bit 8.4.4 N Bit 8.4.5 T Bit 8.4.6 IV Bit 8.4.7 FU Bit 8.4.8 DV Bit 8.5 Permanent Exception Enables 8.5.1 Divide by Zero 8.5.2 Floating Overflow 8.6 Instruction and Addressing Mode Formats 8.6.1 Opcode Formats 8.6.2 Operand Specifiers 8.7 General Addressing Mode Formats 8.7.1 Register Mode 8.7.2 Register Deferred Mode 8.7.3 Autoincrement Mode 8.7.4 Autoincrement Deferred Mode 8.7.5 Autodecrement Mode 8.7.6 Displacement Mode 8.7.7 Displacement Deferred Mode 8.7.8 Literal Mode 8.7.9 Index Mode 8.8 Summary of General Mode Addressing 8.8.1 General Register Addressing 8.8.2 Program Counter Addressing 8.9 Branch Mode Addressing Formats 9 VAX Instruction Set 9.1 Introduction to the VAX Instruction Set 9.2 Instruction Descriptions 9.2.1 Integer Arithmetic and Logical Instructions ADAWI ADD ADWC ASH BIC BIS BIT CLR CMP CVT DEC DIV EDIV EMUL INC MCOM MNEG MOV MOVZ MUL PUSHL ROTL SBWC SUB TST XOR 9.2.2 Address Instructions MOVA PUSHA 9.2.3 Variable-Length Bit Field Instructions CMP EXT FF INSV 9.2.4 Control Instructions ACB AOBLEQ AOBLSS B BB BB BB BLB BR BSB CASE JMP JSB RSB SOBGEQ SOBGTR 9.2.5 Procedure Call Instructions CALLG CALLS RET 9.2.6 Miscellaneous Instructions BICPSW BISPSW BPT HALT INDEX MOVPSL NOP POPR PUSHR XFC 9.2.7 Queue Instructions 9.2.7.1 Absolute Queues 9.2.7.2 Self-Relative Queues 9.2.7.3 Instruction Descriptions INSQHI INSQTI INSQUE REMQHI REMQTI REMQUE 9.2.8 Floating-Point Instructions 9.2.8.1 Introduction 9.2.8.2 Overview of the Instruction Set 9.2.8.3 Accuracy 9.2.8.4 Instruction Descriptions ADD CLR CMP CVT DIV EMOD MNEG MOV MUL POLY SUB TST 9.2.9 Character String Instructions CMPC LOCC MATCHC MOVC MOVTC MOVTUC SCANC SKPC SPANC 9.2.10 Cyclic Redundancy Check Instruction CRC 9.2.11 Decimal String Instructions 9.2.11.1 Decimal Overflow 9.2.11.2 Zero Numbers 9.2.11.3 Reserved Operand Exception 9.2.11.4 UNPREDICTABLE Results 9.2.11.5 Packed Decimal Operations 9.2.11.6 Zero-Length Decimal Strings 9.2.11.7 Instruction Descriptions ADDP ASHP CMPP CVTLP CVTPL CVTPS CVTPT CVTSP CVTTP DIVP MOVP MULP SUBP 9.2.12 The EDITPC Instruction and Its Pattern Operators EDITPC EO$ADJUST_INPUT EO$BLANK_ZERO EO$END EO$END_FLOAT EO$FILL EO$FLOAT EO$INSERT EO$LOAD_ EO$MOVE EO$REPLACE_SIGN EO$_SIGNIF EO$STORE_SIGN 9.2.13 Other VAX Instructions PROBE x CHM REI LDPCTX SVPCTX MTPR MFPR BUG 10 VAX VECTOR ARCHITECTURE 10.1 Introduction to VAX Vector Architecture 10.2 VAX Vector Architecture Registers 10.2.1 Vector Registers 10.2.2 Vector Control Registers 10.2.3 Internal Processor Registers 10.3 Vector Instruction Formats 10.3.1 Masked Operations 10.3.2 Exception Enable Bit 10.3.3 Modify Intent Bit 10.3.4 Register Specifier Fields 10.3.5 Vector Control Word Formats 10.3.6 Restrictions on Operand Specifier Usage 10.3.7 VAX Condition Codes 10.3.8 Illegal Vector Opcodes 10.4 Assembler Notation 10.5 Execution Model 10.5.1 Access Mode Restrictions 10.5.2 Scalar Context Switching 10.5.3 Overlapped Instruction Execution 10.5.3.1 Vector Chaining 10.5.3.2 Register Conflict 10.5.3.3 Dependences Among Vector Results 10.6 Vector Processor Exceptions 10.6.1 Vector Memory Management Exception Handling 10.6.2 Vector Arithmetic Exceptions 10.6.3 Vector Processor Disabled 10.6.4 Handling Disabled Faults and Vector Context Switching 10.6.5 MFVP Exception Reporting Examples 10.7 Synchronization 10.7.1 Scalar/Vector Instruction Synchronization (SYNC) 10.7.2 Scalar/Vector Memory Synchronization 10.7.2.1 Memory Instruction Synchronization (MSYNC) 10.7.2.2 Memory Activity Completion Synchronization (VMAC) 10.7.3 Other Synchronization Between the Scalar and Vector Processors 10.7.4 Memory Synchronization Within the Vector Processor (VSYNC) 10.7.5 Required Use of Memory Synchronization Instructions 10.7.5.1 When VSYNC Is Not Required 10.8 Memory Management 10.9 Hardware Errors 10.10 Vector Memory Access Instructions 10.10.1 Alignment Considerations 10.10.2 Stride Considerations 10.10.3 Context of Address Specifiers 10.10.4 Access Mode 10.10.5 Memory Instructions VLD VGATH VST VSCAT 10.11 Vector Integer Instructions VADDL VCMPL VMULL VSUBL 10.12 Vector Logical and Shift Instructions VBIC, VBIS, and VXOR VSL 10.13 Vector Floating-Point Instructions 10.13.1 Vector Floating-Point Exception Conditions 10.13.2 Floating-Point Instructions VADD VCMP VVCVT VDIV VMUL VSUB 10.14 Vector Edit Instructions VMERGE IOTA 10.15 Miscellaneous Instructions MFVP MTVP VSYNC A ASCII Character Set B Hexadecimal/Decimal Conversion B.1 Hexadecimal to Decimal B.2 Decimal to Hexadecimal B.3 Powers of 2 and 16 C VAX MACRO Assembler Directives and Language Summary C.1 Assembler Directives C.2 Special Characters C.3 Operators C.3.1 Unary Operators C.3.2 Binary Operators C.3.3 Macro String Operators C.4 Addressing Modes D Permanent Symbol Table Defined for Use with VAX MACRO E Exceptions That May Occur During Instruction Execution E.1 Arithmetic Traps and Faults E.1.1 Integer Overflow Trap E.1.2 Integer Divide-by-Zero Trap E.1.3 Floating Overflow Trap E.1.4 Divide-by-Zero Trap E.1.5 Floating Underflow Trap E.1.6 Decimal String Overflow Trap E.1.7 Subscript-Range Trap E.1.8 Floating Overflow Fault E.1.9 Divide-by-Zero Floating Fault E.1.10 Floating Underflow Fault E.2 Memory Management Exceptions E.2.1 Access Control Violation Fault E.2.2 Translation Not Valid Fault E.3 Exceptions Detected During Operand Reference E.3.1 Reserved Addressing Mode Fault E.3.2 Reserved Operand Exception E.4 Exceptions Occurring as the Consequence of an Instruction E.4.1 Reserved or Privileged Instruction Fault E.4.2 Operand Reserved to Customers Fault E.4.3 Instruction Emulation Exceptions E.4.4 Compatibility Mode Exception E.4.5 Change Mode Trap E.4.6 Breakpoint Fault E.5 Trace Fault E.5.1 Trace Operation When Entering a Change Mode Instruction E.5.2 Trace Operation Upon Return From Interrupt E.5.3 Trace Operation After a BISPSW Instruction E.5.4 Trace Operation After a CALLS or CALLG Instruction E.6 Serious System Failures E.6.1 Kernel Stack Not Valid Abort E.6.2 Interrupt Stack Not Valid Halt E.6.3 Machine Check Exception FIGURES 6-1 Using Transfer Vectors 10-1 Vector Register 10-2 Vector Length Register (VLR) 10-3 Vector Mask Register (VMR) 10-4 Vector Count Register (VCR) 10-5 Vector Processor Status Register (VPSR) 10-6 Vector Arithmetic Exception Register (VAER) 10-7 Vector Memory Activity Check (VMAC) Register 10-8 Vector Translation Buffer Invalidate All (VTBIA) Register 10-9 Vector State Address Register (VSAR) 10-10 Vector Control Word Operand (cntrl) 10-11 Vector Control Word Format 10-12 Memory Management Fault Stack Frame (as Sent by the Vector Processor) 10-13 Encoding of the Reserved Operand E-1 Compatibility Mode Exception Stack Frame TABLES 3-1 Special Characters Used in VAX MACRO Statements 3-2 Separating Characters in VAX MACRO Statements 3-3 Unary Operators 3-4 Binary Operators 5-1 Addressing Modes 5-2 Floating-Point Literals Expressed as Decimal Numbers 5-3 Floating-Point Literals Expressed as Rational Numbers 5-4 Index Mode Addressing 6-1 Summary of General Assembler Directives 6-2 Summary of Macro Directives 6-3 .ENABLE and .DISABLE Symbolic Arguments 6-4 Condition Tests for Conditional Assembly Directives 6-5 Operand Descriptors 6-6 Program Section Attributes 6-7 Default Program Section Attributes 6-8 .SHOW and .NOSHOW Symbolic Arguments 8-1 Representation of Least-Significant Digit and Sign in Zoned Numeric Format 8-2 Representation of Least-Significant Digit and Sign in Overpunch Format 8-3 Floating-Point Literals Expressed as Decimal Numbers 8-4 Floating-Point Literals Expressed as Rational Numbers 8-5 General Register Addressing 8-6 Program Counter Addressing 9-1 Summary of EDITPC Pattern Operators 9-2 EDITPC Pattern Operator Encoding 10-1 Description of the Vector Processor Status Register (VPSR) 10-2 Possible VPSR<3:0> Settings for MTPR 10-3 State of the Vector Processor 10-4 VAER Exception Condition Summary Word Encoding 10-5 IPR Assignments 10-6 Description of the Vector Control Word Operand 10-7 Dependences for Vector Operate Instructions 10-8 Dependences for Vector Load and Gather Instructions 10-9 Dependences for Vector Store and Scatter Instructions 10-10 Dependences for Vector Compare Instructions 10-11 Dependences for Vector MERGE Instructions 10-12 Dependences for IOTA Instruction 10-13 Dependences for MFVP Instructions 10-14 Miscellaneous Dependences 10-15 Possible Pairs of Read and Write Operations When Scalar/Vector Memory Synchronization (M) or VSYNC (V) Is Requiredt 10-16 Encoding of the Exception Condition Type (ETYPE) C-1 Assembler Directives C-2 Special Characters Used in VAX MACRO Statements C-3 Summary of Unary Operators C-4 Summary of Binary Operators C-5 Macro String Operators C-6 Summary of Addressing Modes D-1 Opcodes (Alphabetic Order) and Functions D-2 One_Byte Opcodes (Numeric Order) D-3 Two_Byte Opcodes (Numeric Order) E-1 Arithmetic Exception Type Codes E-2 Compatibility Mode Exception Type Codes